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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-23005-3E
ASSP
CMOS
3 V Single Power Supply Audio Interface Unit (AIU)
MB86437
s DESCRIPTION
The FUJITSU MB86437 is an AIU (audio interface unit) LSI for +3 V single-power source digital telephone devices, manufactured using CMOS process technology. The codec transmission filter characteristics meet G.712 standards, and can handle input and output in A-Law, -Law and linear conversion modes. The MB86437 also contains the necessary DTMF, microphone and receiver amps for telephone devices.
s FEATURES
* +3 V single power supply * Low power consumption: muting settings for each operating mode Normal operation : 5.0 mA TYP Standby mode : 0.5 A TYP * On-chip codec filter meets G.712 standards * Selection of codec companding law (A-law, -law, 14 bit linear) * On-chip low-noise microphone amp (2-channel) (0 to 35 dB amplification) * On-chip receiver speaker amps (32 BTL type: 10 mW MIN) * On-chip earphone speaker amps (32 single type: 5 mW MIN)
(Continued)
s PACKAGE
48 pin, Plastic LQFP
(FPT-48P-M05)
MB86437
(Continued)
* * * * * On-chip electronic volume gain adjustments (sending, receiving, tone) On-chip accessory input/output circuits DTMF generator function Service tone generation CMOS compatible input/output
s PIN ASSIGNMENT
48 1 Index
(TOP VIEW)
37 36
12 13 (FPT-48P-M05) 24
25
2
MB86437
s PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Symbol SWI SWO RAUD VD1 JEAR EAR XEAR VS1 TONE TBO TBI PTBO MDI VD2 DSCK EXSD TAUD MICO MIC XMIC JMIC JMICO VS2 SGC VS4 SGI I/O I/O I/O O P O O O G O O I O I P I/O I/O I/O O I I I O G O G I A/D A/D A/D A A A A A A A A A A A A A A A A A A A A A A A A Description I/O pin for analog switch SW12 The standard on resistance for the analog switch is 500 . I/O pin for analog switch SW12 Connected to pin 1 via switch SW12. Output pin for the received audio signal to the external speaker or for testing. Power supply pin for reception. Supply a voltage between 2.7 V and 3.6 V. Amplifier output pin for the earphone speaker. Can output 5 mW for a 32 load. Amplifier output pin for the receiver speaker. Internal BTL connection to XEAR. The maximum output for a 32 load between EAR and XEAR is 10 mW. Amplifier output pin for the receiver speaker. BTL connection to XEAR. Ground pin for reception. Set to 0 V. Amplifier output pin for the tone speaker. The output can be set to normal mode, ground, or high impedance. AMP4 output pin. Pair high pass filter with TBI so that there is no DC offset at the speaker. AMP4 inverted (-) input pin PCM reception, tone addition output Pin used to add an analog input signal to the tone section or apply an envelope to the tone. Required functions can be selected by controlling SW16. Setting SW16 off sets the input impedance to approximately 140 k and setting SW16 on sets the input impedance to approximately 210 k. Power supply pin for reception. Supply a voltage between 2.7 V and 3.6 V. Can be connected to EXSD and TAUD by path switching. Can be connected to DSCK and TAUD by path switching. Can be connected to EXSD and DSCK by path switching. Output pin for mike amplifier [1] Inverted input pin (-) for mike amplifier [1] Non-inverted input pin (+) for mike amplifier [1] Inverted input pin (-) for mike amplifier [2] Output pin for mike amplifier [2] Ground pin for transmission. Set to 0 V. Pin for connecting the bypass capacitor for the signal ground potential generation circuit. Connect a capacitor between SGC and VS2. Ground pin for A/D and D/A. Set to 0 V. General-purpose amplifier. To use, connect to SGO.
(Continued)
3
MB86437
(Continued)
Pin No. 27 28 29 30 31 32 33 34 Symbol SGO STA BBO BTPI BTPO VD3 DIN DOUT I/O O O O I O P I O A/D A A A A A D D D Description General-purpose amplifier output pin. The signal can also go to JEAR via SW15. Transmission analog signal output via SW1. Connect to AMP4 when performing sidetone addition for reception. The standard on resistance for the analog switch is 500 . Transmission analog signal output pin Inverted input pin (-) for the PCM ENCODE section input op-amp Output pin for the PCM ENCODE section input op-amp Power supply pin for transmission. Supply a voltage between 2.7 V and 3.6 V. PCM signal input pin. The signal is clocked in on the falling edge of CLK. CMOS interface. PCM signal output pin. The signal is clocked out on the rising edge of CLK. After data output, becomes fixed at the "H" level if PLL synchronization is lost or a power-down occurs. CMOS interface. Transmission and reception sync signal input pin for the PCM CODEC section. The operating clock frequency is 8 kHz. CMOS interface. Fixing at "H" or "L" causes part of the CODEC section to power-down. Input pin for setting the bit rate for the transmission and reception PCM signals. The data rate can be selected from 64 kHz to 3.152 MHz for -law or A-law operation, or from 128 kHz to 3.152 MHz for linear operation. Fixing at "H" or "L" causes part of the CODEC section to power-down. CMOS interface. Clock input pin for tone generation. The internal clock divided by one or two (set by D4D3 of address 01110) can be used as the tone CLK. CMOS interface. Digital power supply pin. Supply a voltage between 2.7 V and 3.6 V. 10-bit serial data input pin. CMOS interface. This data sets the electronic volume, path, and tone settings. Write clock input pin for the 10-bit serial data. CMOS interface. SRD is clocked in the rising edge. Strobe signal for the serial data latch. Latches on "L". CMOS interface. Reset signal input pin for the digital circuits. CMOS interface. L: Initialize internal latches. H: Normal Latch output pin for external control. Outputs D0 of address 01000. CMOS interface. Latch output pin for external control. Outputs D1 of address 01000. CMOS interface. Latch output pin for external control. Outputs D2 of address 01000. CMOS interface. Latch output pin for external control. Outputs D3 of address 01000. CMOS interface. Power-down control signal input pin. CMOS interface. Powers down all circuits regardless of register settings. Digital ground pin. Set to 0 V.
35
SYNC
I
D
36
CLK
I
D
37 38 39 40 41 42 43 44 45 46 47 48 4
TCLK VD4 SRD SRC STB XPRST LO0 LO1 LO2 LO3 PS VS3
I P I I I I O O O O I G
D D D D D D D D D D D D
MB86437
s BLOCK DIAGRAM
SGC (24) BTPO (31) BTPI (30) SGI (26) SGO (27) BBO (29) STA (28) VS 1 (8) VS 2 (23) VS 3 (48) VS 4 (25)
- +
VREF
SW1 0 dB (RST) EV0 (Invert) 4bit AMP1 SGC SW4
- +
generator AMP5 AO SGC SGC VREF generator block
0 dB
- +
SW3
- +
Microphone amp (1)
MICO (18) MIC (19) XMIC (20) JMICO (22) JMIC (21)
DOUT (34) SYNC (35) CLK (36) DIN (33)
A/D
BPF AMP2
- +
-7 to 8 dB 1 dB step SGC Transmitting block
PLL 512 K D/A LPF
Codec block 0 dB (RST) EV1 4bit 0 dB SW13 -7 to 8 dB 1 dB step
- +
Microphone amp (2) SW5
SGC
0 dB (RST) EV2 (Invert)
SW10 SW11
TCLK (37) MDI (13)
SINGLE: -14 dBv Tone generator block DUAL: -14 dBv -15 dB 15 dB (RST) (RST) DUAL TONE EV4 EV3 (Invert) + 3bit 4bit ATT SW16 -30 to 0 dB 8 to 23 dB -15 dB 5 dB step 1 dB step
3bit AMP3 SGC -15 to 15 dB, 5 dB step 0 dB SW8b
- +
SW12
-14 dB (RST) EV5 3bit 0 dB -18 to -11dB 1 dB step SW 2
PD SGC SW8a -8 dB (RST) -14 to 0 dB EV6 2 dB step 3bit 0 dB SW6b SGC SW6a
- +
TAUD (17) EXSD (16) DSCK (15) PTBO (12) SWI (1) SWO (2) RAUD (3)
PD 0 dB
EAR (6)
TBO (10) TBI (11) SGC
- +
Receiver speaker drive block -3 dB (RST) -9 to 0 dB 3 dB step EV7 2bit 0 dB SGC
- +
PD XEAR (7)
AMP4
SW15 Receiving block AO
SW7b SGC
- +
PD
JEAR (5)
Earphone speaker drive block EV8 1bit EV9 1bit
SW7a
SRD (39) SRC (40) STB (41)
Control block CONTROL LOGIC
10 dB (RST) 0 dB, 10 dB 6 dB (RST) 0 dB, 6 dB
0 dB SW9b
-
PSAVE
0 dB
SW9c
+
PD
SW14
TONE (9)
SGC SW9a Tone speaker drive block
Electronic volume: * (RST) indicates the value for reset * (inverting) indicates the inverted phase between input and output. : Input/output : VDD : GND
XPRST LO0 LO1 LO2 LO3 (42) (43) (44) (45) (46)
: Digital input
PS (47)
VD1 (4) VD2 (14) VD3 (32) VD4 (38)
: Analog input : Analog output
: Digital output
5
MB86437
s FUNCTIONAL DESCRIPTION
1. Register Settings The MB86437 IC chip controls all electronic volume, switch, tone generator circuit and power-down control circuit by means of the SRD, STB and SRC input. (1) Mode setting The data format consists of 10 bits of serial data. The first 5 bits (A4 to A0) are the address and the next 5 bits (D4 to D0) are data. SRD is clocked in on the rising edge of SRC and latched when STB is "L". During power-down, the register is not reset and writing to the register is possible. A reset and data initialization occurs when XPRST is "L". Data Setting After a Reset D4 D3 D2 D1 D0 A00 00000 A01 00001 A02 00010 A03 00011 A04 00100 Test mode EV0 gain EV1 gain EV2 gain Transmit mute 1 (SW3, 4, 5) Receive mute 1 (SW6b, 7b, 8b, 9b, 9c) SW8, 3, 4, 5 mute 2 0 0 0 0 1 1 0 1 1 0 D4 D3 Data Meaning D2 D1 X X D0
Data Address
Meaning
0 00000: Normal operation (writing prohibited)
1 X EV0 [0000: -7 dB to 1111: 8 dB, step 1 dB, Reset: 0 dB] 1 X EV1 [0000: -7 dB to 1111: 8 dB, step 1 dB, Reset: 0 dB] 1 1X X
XX0
EV2 [000: -15 dB to 111: 15 dB, step 5 dB, Reset: 0 dB] X X Transmit mute (SW3, 4, 5) 1: Mute 1 0: No mute
X 0 X X X 0 Receive mute (SW6b, 7b, 8b, 9b, 9c) 1: Mute 1 0: No mute 1X1 1 1 SW8 X 1: Mute 2 0: No mute Valid when D4 of A04 is "0" 1 EV7 [00: -9 dB to 11: 0 dB, step 3 dB, Reset: -3 dB] 0X SW2 1: ON 0: OFF L03
A05 00101
SW4 SW5 SW3 1: Mute 2 1: Mute 2 1: Mute 2 0: No mute 0: No mute 0: No mute Valid when D0 of A04 is "0" SW9b9c SW6b SW7b 1: Mute 2 1: Mute 2 1: Mute 2 0: No mute 0: No mute 0: No mute Valid when D4 of A04 is "0" SW11 1: ON 0: OFF L02 SW12 1: ON 0: OFF L01 SW10 1: ON 0: OFF L00 X
A06 00110
EV7 gain/SW7b, 1 9b, 9c, 6b mute 2
0
1
1
A07 00111
SW2, 11, 12, 10 X 1 control Digital parallel output EV3 gain X0 0 1
0
0
A08 01000 A09 01001
0 1
0
0X
1 X EV3 [0000: 8 dB to 1111: 23 dB, step 1 dB, Reset: 15 dB]
(Continued)
6
MB86437
(Continued)
Data Address
Meaning Tone [1] setting
Data Setting After a Reset D4 D3 D2 D1 D0 D4 D3 0 0 0 0
Data Meaning D2 D1 D0
A0A 01010
0 Tone 1 na = a7 x 27 + a6 x 26 + ... + a1 x 2 + a0 waveform 1: Square wave a7 a6 a5 a4
0: Sine wave
A0B 01011 A0C 01100 Tone [2] setting
X0 0 0
0 0
1 0
0X
a3
7
a2
6
a1
a0
0 Tone 2 nb = b7 x 2 + b6 x 2 + ... + b1 x 2 + b0 waveform 1: Square b6 b5 b4 wave b7
0: Sine wave
A0D 01101 A0E 01110 Tone waveform setting (for tones [1] and [2])
X0 0
0
1
0X 0
b3
b2
b1 Tone [1] control 1: Generate 0: Stop
b0 Tone [2] control 1: Generate 0: Stop
0X0
Divide ratio Division X ratio (TCLK/N) (M) 00 TCLK/1 12 divisions 01 TCLK/1 24 divisions 10 TCLK/2 24 divisions 11 Use prohibited X X
A0F 01111
CODEC compression rule
XXX0
0X
CODEC companding law
00: -LAW 01: Linear 10: A-LAW 11: Use prohibited
A10 10000
PD control and 0 SW14 control for CODEC, TONE, SGO, and transmission (TX)
0
0
0
0 CODEC PD TONE PD SGO PD Transmit1: PD 1: PD 1: PD ter PD 0: Operate 0: Operate 0: Operate 1: PD 0: Operate
SW14 1: TONE output 0 V 0: Operate
A11 10001
PD control for 0X0 RAUD, JEAR, TONE, and EAR
0
0 RAUD PD X (SW8a) 1: Independent 0: Linked
JEAR PD (SW7a) 1: Independent 0: Linked
TONE PD (SW9a) 1: Independent 0: Linked
EAR PD (SW6a) 1: Independent 0: Linked
Independent: Do not power-down corresponding amplifier in conjunction with mute. Linked: Power-down corresponding amplifier in conjunction with mute. A12 10010 DOUT/SW1, 13, 9b, 9c 0 0 0 1 1 DOUT 1: Fixed at "H" 0: Operate SW1 mute SW13 1: Mute mute 0: No mute 1: Mute 0: No mute SW9b mute 0: Mute 1: No mute SW9c mute 0: Mute 1: No mute
The tone frequencies are as follows. (fa and fb are the frequencies of tones [1] and [2] respectively.) (fin = TCLK input frequency (512 kHz recommended when N = 1, M = 12, 1024 kHz recommended when N = 1, M = 24 fin/(N x M) = 42.667 kHz), N: Divide ratio (1 or 2), M: Number of divisions (12 or 24)) fa = (fin/(N x M))/(na + 1), fb = (fin/(N x M))/(nb + 1) (Continued) 7
MB86437
(Continued)
Data Address
Meaning EV8, EV6 gain
Data Setting After a Reset D4 D3 D2 D1 D0 D4 X D3 1X0 1 1 EV8 gain 1: 10 dB 0: 0 dB 1X 1 EV9 gain 1: 6 dB 0: 0 dB 0X
Data Meaning D2 D1 D0
A13 10011
EV6 [000: -14 dB to 111: 0 dB, step 2 dB, Reset: -8 dB] EV4 [000: -30 dB to 111: 0 dB, step 5 dB, Reset: -15 dB] EV5 [000: -11 dB to 111: -18 dB, step 1 dB, Reset: -14 dB] X SW15 1: AMP5 0: AMP4 X SW16 * 1 1: Envelope 0: ATT All circuits PD 1: Normal 0: PD
A14 10100 A15 10101
EV4 gain EV9, EV5 gain
XX0 1X0
1 1
X X
A16 10110
SW15, 16 control
XXX0
X
A17 10111
All PD
XXXX1X
X
X
Notes: 1. When unused, connect the MDI input to OPEN or SGC. When using ATT, an SGC-centered signal or capacitive coupling is required (to prevent an offset). 2. Set X to 0. 3. Set to initial value by a reset (____ section).
8
MB86437
(2) Transmitting audio mute settings Switches SW1, SW3, SW4, SW5, SW10, and SW11 have the following functions. Address 00100 signals have priority. Setting Address A4 to A0 00100 D4 to D0 -***1 -***0 Data bit -***0 -***0 -***0 -***0 -***- : ON, A4 to A0 00101 D4 to D0 -*--- -*01- -*10- -*--0 -*--1 -*--1 -*--- A4 to A0 00111 D4 to D0 *---- *---- *---- *-0-0 *-0-1 *-1-0 *---- A4 to A0 10010 D4 to D0 ----- ----- ----- ----- ----- ----- -1--- SW1 SW3 SW4 SW5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SW1 SW1 0 1 -- -- -- -- -- -- Microphone amp [1], [2] mute Microphone amp [2] mute Microphone amp [1] mute Switching setting Remarks
: OFF, -- : not determined
(3) Receiving audio mute settings Switches SW6b, SW7b, SW8b, SW9b, SW9c, and SW12 have the following functions. Address 00100 signals have priority. Setting Address A4 to A0 00100 D4 to D0 1***- 0***- 0***- Data bit 0***- 0***- 0***- 0***- 0***- 0***- : ON, A4 to A0 00101 D4 to D0 -*--- 1*--- 0*--- -*--- -*--- -*--- -*--- -*--- -*--- A4 to A0 00110 D4 to D0 ----- ----- --1-- --01- ---0- ---0- ----1 ----0 ----- A4 to A0 00111 D4 to D0 *---- *---- *---- *---- *---- *---- *---- *0--- *1--- A4 to A0 10010 D4 to D0 ----- ----- ----- ----- ---01 ---10 ----- ----- ----- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SW6 SW7 SW8 SW9 SW9 SW1 b b b b c 2 -- -- -- -- -- -- -- Switching setting
Remarks
: OFF, -- : not determined
9
MB86437
(4) Electronic volume controls There are ten different electronic volume controls, EV0 through EV9, with the following specifications. Electronic volume control settings are made by the SRD, SRC and STB signals, and setting values are reset by the XPRST signal. Table 1 Relation of Volume Control Data bit Values to Gain Address 00001 Data Code EV0 00010 EV1 00011 EV2 01001 EV3 10100 EV4 10101 EV5 10011 EV6 00110 EV7 10011 EV8 10101 EV9
NonNonNonNonNonNonNonInverte Inverte Inverte Inverte Inverte Inverte Inverte Inverte Inverte Unit Inverte d d d D4 D3 D2 D1 d d d d d d d D0 D4 to D4 to D2 to D4 to D2 to D2 to D2 to D4 to D4 D4 D1 D1 D0 D1 D0 D1 D0 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 -15 -10 -5 0 5 10 15 15 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 -11 -12 -13 -14 -15 -16 -17 -18 -14 -12 -10 -8 -6 -4 -2 0 -30 -25 -20 -15 -10 -5 0 0 -11 -12 -13 -14 -15 -16 -17 -18 -14 -12 -10 -8 -6 -4 -2 0 -9 -9 -9 -9 -9 -9 -9 -9 -6 -6 -6 -6 -6 -6 -6 -6 -3 -3 -3 -3 -3 -3 -3 -3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
10 10 10 10 10 10 10 10
6 6 6 6 6 6 6 6
dB
Notes: * Each setting value is determined in relation to the initial setting value. * Returns to initial value at reset ( parts) * The "Inverted" and "Non-Inverted" columns indicate the I/O phase. * Settings with no gain figure listed are undefined.
10
MB86437
(5) Tone generation circuit This section describes the frequency settings and output control. * Tone frequency control register The clock used to generate tones is the clock input from TCLK divided by 1 or 2. The divide ratio is set by the data at address 01110. Also, 12 division and 24 division modes are available to generate a smooth frequency even at low frequencies. Table 2 Register Control for the TONE Clock Frequency Address 01110 D4 0 0 1 1 D3 0 1 0 1 Tone Generation Clock (fIN) Frequency input to TCLK Frequency input to TCLK Frequency input to TCLK divided by 2 Prohibited Waveform Division 12 divisions 24 divisions 24 divisions
The following formula specifies the frequencies that can be set by the tone frequency control register. Set frequency f = fIN/(M x (1 + n)), M = division mode (12 or 24) n = 4, 5, ..., 255 (fIN: Tone generation clock) fIN = 4 MHz max. Therefore, the range of available frequencies in 12 division mode and fIN = 512 kHz, and in 24 division mode and fIN = 1024 kHz is: fmin = 167 Hz, fmax = 8533 Hz Table 3 lists the frequency settings for all the standard DTMF frequencies. Table 3 Tone Frequency Register Control (Setting: 12 divisions and fIN = 512 kHz, or 24 divisions and fIN = 1024 kHz) Standard Frequency (Example of generated frequency) 400 Hz 2000 Hz 697 Hz Low tones D T M F High tones 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz Address 01010/01100 Data D4 D3 D2 D1 D0 -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 1 Address 01011/01101 Data D4 D3 D2 D1 D0 1 0 1 0 0 1 0 1 1 1 0 1 1 1 0 1 0 1 1 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 n Error
Tone Type
Set Frequency 398.7 Hz 2031.7 Hz 699.4 Hz 775.7 Hz 853.3 Hz 948.1 Hz 1219.0 Hz 1333.3 Hz 1471.3 Hz 1641.0 Hz
Service tones (Single tone)
106 20 60 54 49 44 34 31 28 25
-0.32% 1.56% 0.34% 0.74% 0.15% 0.75% 0.82% -0.20% -0.38% 0.48%
Notes: * Settings are shown in binary notation. * Error is the error between the set frequency and standard frequency. * Set n to 4 or higher and set a frequency of 5 kHz or less.
11
MB86437
* Tone output waveform The D4 data bit at address 01010, 01100 may be used to select either sine-wave or trapezoidal waveforms for tone output.
VH
D4 = 0 Sine wave output
VL 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5
VH D4 = 1
Trapezoidal wave
output VL
* Tone output control Tone output is controlled by addresses 01110 and 00111. Provided TCLK does not stop, sine wave output always halts close to zero. Also, SW2 controls output muting.
Address 01110 DATA - - - D1 - (Tone [1] control) Address 01110 DATA - - - - D0 (Tone [2] control) Address 00111 DATA - - - D1 - (SW2 control) Mute set by SW2 Waveform halts at zero crossover point.
PTBO output (sine wave mode)
SGC
Tone section output SGC (sine wave mode) Single tone Dual tone
Waveform halts at zero crossover point.
Single tone : Disable
12
MB86437
* Tone envelope Even if the tone halts at close to zero, changes in the DC voltage can still occur can be audible. Using SW16 for tone control enables the voltage level for tone generation to be controlled. The waveform amplitude characteristics have the following general relationships. Va = 2 x (0.47 - 0.12 x Vl) (Vl: MDI voltage, Va = Tone amplitude)
R5 Control clock R4
V1
210 k MDI
SW 16
C1
130 k
25 k
VR - +
Tone output
Vl
Vh
MDI AMP 3
SGC
For a cut off frequency of 8.3 Hz, control clock of 0 to 3 V, and SGC = 1.5 V, the envelope ratio and resistor and capacitor values are as follows. Envelope Ratio Aim Value -3 dB -4 dB -5 dB -6 dB Recommended Values R4 33 k 47 k 82 k 270 k R5 22 k 18 k 15 k 15 k C1 1.5 F 1.5 F 1.5 F 1.5 F Vh, Vl Voltages Max. (Vh) 0.828 V 0.824 V 0.810 V 0.790 V Min. (Vl) 0.584 V 0.516 V 0.448 V 0.400 V Envelope Ratio Calculated Value -3.13 dB -4.05 dB -5.15 dB -5.91 dB
13
MB86437
(6) CODEC I/O Code companding for -law and A-law is in accordance with CCITT Recommendation G.711. Linear coding uses 14-bit, two's complement code which is output MSB-first. Address 01111 is used to control -law, A-law, and linear code I/O.
SYNC Din, Dout MSB 12 11 10 1 LSB
Table 4 Table of Linear Code vs. Voltage MSB Code LSB 111111 000001 000000 111111 000001 PTBO Standard Voltage (V) 2.2647 to 1.5009 1.5000 1.4991 to 0.7354
01111111 to 00000000 00000000 11111111 to 10000000 (7) Parallel output
LO0 to 3 are general-purpose latch outputs for external control. LO0 to 3 output the data written to address 01000. The outputs are CMOS outputs. Data output continues during power-down.
D3 Address 01000
D2
D1
D0
LO0 LO1 LO2 LO3 (Inside IC)
14
MB86437
2. Analog Input Analog inputs in the MB86437 include the two microphone inputs and the three accessory input. (1) Microphone amps The microphone amps take the incoming signal from the microphones and amplify it to any desired level of gain. The microphone amps are low-noise types for use with capacitor microphones, and are capable of a wide range of amplification. All microphone amps must be AC coupling with capacitors to prevent amplification of DC offset level.
Mike amplifier characteristics (open loop characteristics) 80 Gain (dB) 40 0 -40 10 1K Frequency (Hz) 1M
V DD MICO
- +
MIC XMIC
Capacitor type Mike
(Inside IC)
SGC
AG
(2) Accessory input Direct input from the TAUD to the codec unit is possible through SW5, without passing through the microphone amp. Care must be taken with the input signal in this case, however, because input resistance is not at highimpedance level. Microphone amp output may be added to the signal by using switching controls. In this case, the result will be at the additional output level. In addition, SW10 and SW11 may be used to transmit digital data from the TAUD to EXSD and DSCK, allowing the sending of fax or PC data without modification.
Approximately 100 k 0 dB SW5 TAUD SW10
-
CODEC
+
EXSD SW11 SGC (Inside IC) DSCK
Note: TAUD, EXSD, and DSCK contain no buffers. If not used, TAUD, EXSD and DSCK should be connected to SGC.
15
MB86437
3. Analog Output Relationships The four analog outputs consist of three speaker drivers (for receiver, earphone, and tone) and an accessory output. (1) Speaker driver amps The speaker driver amps consist of one BTL output (the receiver output) and one single output (the earphone output). Also, the sounder driver consists of one single output and the sounder output can be obtained via a transistor. As the speaker amps have high power consumption, separate power-down control is available for each speaker amp. Parameter Output type Load resistance *1 Load capacitance *2 Maximum output power *1: *2: Receiver Speaker Amp (EAR, XEAR) BTL 32 (typ.) 0.1 F 10 mW (min.) Earphone Speaker Amp (JEAR) Single 32 (typ.) 0.1 F 5 mW (min.) Tone Amp (TONE) Single 600 (typ.)
Dynamic speaker A capacitor is required to prevent oscillation.
* Analog output connection example
EV6
_ +
EAR SGC C1 Receiver speaker Dynamic type: 32 (typ)
TBO SGC
- +
XEAR
C1
EV7
- +
JEAR C1
C2
Earphone speaker Dynamic type: 32 (typ)
SGC
EV8 Sounder EV9 EV4 SGC SW 14 (Inside IC) Note: Insert C1 capacitors of approximately 0.1 F to prevent oscillation. C2 is to cut DC.
- +
TONE
16
MB86437
4. Reception Connections This section describes reception connections, sidetone addition, and melody IC connection. (1) Reception connections This describes the connection to the speaker amp for the reception signal. Provide a high-pass filter at AMP4 to prevent a DC offset being applied to the speaker amp. * First-order high-pass filter
EV2 PTBO C1 R1 R2
TBI
- +
AMP4 SGC
TBO
To speaker amplifier
(2) Sidetone addition Sidetone addition is implemented by connecting the STA output and AMP4. In this case, use of a resistor of approximately 100 k at AMP4 is recommended as the SW1 on resistance affects the sidetone gain.
PTBO sw1 STA C1 R1 R2 C1
TBI
- +
R1: Use a resistor of approximately 100 k.
AMP4 SGC
TBO
To speaker amplifier
17
MB86437
(3) Melody IC connection A melody IC can be connected using AMP4. However, the level can be made to vary in the same way as the tone if the MDI pin is used. MDI has an input impedance of approximately 140 k and is not high impedance.
(-14 dBv typ) DUAL TONE (-15 dB) Melody IC MDI SW16 Approximately 140 k SGC
- +
To EV4
(4) JEAR signal selection JEAR can receive a signal from AMP4 or AMP5. This enables a range of applications to be implemented depending on the AMP4 and AMP5 circuit structures. * Example of switching EAR and JEAR
PTBO TBO TBI SGC SGO SGI
- + - +
To EAR AMP4
To JEAR SW15 AMP5
SGC
(5) Preventing a clicking sound when the electronic volume gain is changed or when muting Changing the gain of the electronic volume or muting may result in a clicking sound due to fluctuation in the DC level. In such cases, the following setting is recommended. Set the mode in which powering down the speaker amplifier is not linked with SW6b, 7b, 8b, and 9b (ADDRESS: 10001, DATA: 10111) and mute using SW6b, 7b, 8b, and 9b.
18
MB86437
5. Power-Save Mode This section describes the setting methods and states. (1) Mode setting Power-save mode can be controlled by an external control signal and register setting. The various modes set each block to a power-save state, enabling the power consumption to be reduced. * Power-save mode setting table
Transmission Address PS or
Address
CODEC
EV2 AMP3, 4
AMP5
TONE
VREF
Accessory
10111 D4 D0 D4 D2 D1 D0 D4 D3 D2 D1 D4 D2 D1 D0 STOP
All PD VREF operation SGO PD TONE operation CODEC, TONE PD CODEC operation CODEC SYNC PD Transmission operation Transmission PD
0 1 1 1 1 1 1 1 1 1 1
- - - - - - - - - 1 0 0 1 0
- - - - - - - - - - - - - -
- - - - - - - - - 1 1 1 0 1
- - - - - - - - - 1 1 1 0 1
- - - - - - - - - 1 1 0 0 1
- - - - - - - - - 1 0 1 0 1
- - - - 1 0 0 - - 0 0 0 0 0
- - - 0 1 - - - - 1 1 1 1 1
- 0 1 - - - - - - - - - - -
- - - - - - - 0 1 - - - - -
- - - - - - - - - 0 0 0 1 1
- - - - - - - - - 1 1 0 1 1
- - - - - - - - - 0 0 0 0 1
- - - - - - - - - 0 0 1 0 1
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Reception operation
1 1 1
: Operation enabled,
: Changes depending on address 10001,
: Power-down
Note: Powering down the CODEC or TONE generator powers down the entire reception block.
TONE
Mode
Receiver
00100 00101
00110
10000
10001
Ear Phone
SYNC or CLK
Reception
19
STA
BBO
SGC
JEAR
TONE
BTPO SGO
RAUD
DOUT
EAR, XEAR
TBO, PTBO
MICO, JMICO
MB86437
D4 D0 D4 D2 D1 D0 D2 D1 D0 D3 D4 D3 D2 D1 D0 D4 D2 D1 D0 D4 D3 D2 D1 D0
All PD 1 0 1 11 1 111 0011 S 1 1100 1 S S S---- S-----
0
H* --- --- -- -H-
Reception mute
1
1
(2) Output pin states in each mode
SGO PD
1
--------- R---R
CODEC, TONE PD 1
1
Transmission PD 0 1 0 0 111 0 0 0 1 1
1
-----
R
R - 1
---
Transmission halt
-
-----------H- ----- ----- S - SS- STO --------- P ---- --- --- --- -H-
1
Transmission mute
1
CODEC SYNC PD 0
1
CODEC operation 0
1
-
TONE operation
1
---- 11 1
---- ---S----- ---G-----
--- --- ---
TONE mute
1
: High impedance, S: Signal ground, R: Connected to signal ground via high resistance, : Normal operation * : Depends on value of address 01000, G: Ground output, R1: Connected to signal ground via high resistance when SW1 is on. H : High level output
Address Output Pin State LO0 to 3 00101 00110 00111 10000 10001 10010 SYNC or CLK
20 -
Mode
PS 00100 or Address 10111
TONE GND
1
MB86437
s TIMING CHART
(1) Codec-Related Signals
[1] [2] [3] [4] [5] [6] [7] [8] [13] [14]
CLK
fC fS*
SYNC
i
ii
iii
iv
v
vi
vii
viii
Xiii Xiv
DOUT
1
2
3
4
5
6
7
8
13 14
DIN
(1) (2) (3) A-Iaw ( -law [Enlarged view] (1) [1] [2] ) (3) (14bit-linear)
CLK
t XS t SX
SYNC
t WSH i ii
DOUT
t CO (2) [5] [6] t ZD
CLK
tF 5 tR t DR 6 t RD
DIN
(3)
( [13] ) [7]
( [14] ) [8] tWCH t WCL vii t CO viii t DZ
CLK
DOUT
t DF
*: From first CLK Down to second CLK Down, SYNC = H.
21
MB86437
(2) Microcomputer Data-Related Signals
XPRST t WRE A4 SRD A3 A2 A1 A0 D4 D3 D2 D1 D0
SRC f SC STB
LO 0 to 3 (1) [Enlarged view] (1) SRD D1 SRC t WL t SCB STB t DS D0 t HCB t WH t SSC t HSC
LO 0 to 3 t LD
22
MB86437
s ABSOLUTE MAXIMUM RATINGS (See WARNING)
Parameter Power supply voltage Analog input voltage Digital input voltage Storage temperature Symbol VDD VAIN VDIN Tstg Rating Min. -0.3 -0.3 -0.3 -55 Max. +6.0 VDD + 0.3 VDD + 0.3 +125 Unit V V V C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
s RECOMMENDED OPERATING CONDITIONS
Parameter Operating temperature Power supply voltage "H" level digital input voltage "L" level digital input voltage Analog output load resistance Analog output load capacity Analog output load resistance* Analog output load capacity*1 Analog output load resistance*1 Analog output load capacity*1 Analog output load resistance Analog output load capacity Analog output load resistance Analog output load capacity Analog output load resistance Analog output load capacity Analog output voltage Analog input voltage TCLK frequency *1: *2:
1
Symbol Ta VDD VH VL RLB CLB CLS RLE CLE RLJ CLJ RLT CLT RLM CLM RLM CLM VAOUT VAIN FTCLK
Pin name -- VD1, VD2, VD3 All digital input pins *2 BTPO, BBO, PTBO, TBO, SGO Between SGC-VS4 Between EAR-XEAR EAR, Between XEAR-GND JEAR Between JEAR-GND TONE
Value Min. -20 2.7 VDD x 0.7 0.0 50 -- -- 28 0.1 28 0.1 600 -- 10 -- 5 -- 0.45 1.2 -- Typ. 25 3.0 -- -- -- -- 10 32 -- 32 -- -- -- -- -- -- -- -- 1.5 -- Max. 80 3.6 VDD VDD x 0.3 -- 20 -- -- -- -- -- -- 100 -- 20 -- 20 VDD-0.45 1.8 4.0
Unit C V V V k pF F F F pF k pF k pF V V MHz
MICO, JMICO
RAUD All Amp. output pins All Amp. input pins TCLK
Dynamic typ speakers BTPO, BBO, PTBO, TBO, SGC, SGO
23
MB86437
s ELECTRICAL CHARACTERISTICS
1. DC Characteristics Parameter Power supply current at full power-down mode Power supply current for normal operation (all operation) Digital input current Digital output voltage Input offset voltage Output offset voltage SGC output voltage Symbol IPD All VDP pins IVD2 IIH IIL VOH VOL VFM VFE VSGC RSW RTE Inter-pin resistance RTD RTG RBS RITA Input resistance RIMDA RIMD Analog output off leak IOFH All digital input pins All digital output pins Between MIC-XMIC Between EAR-XEAR SGC Between SWI-SWO Between TAUD-EXSD Between TAUD-DSCK Between TONE-VS Between BBO-STA TAUD MDI MDI RAUD, TONE SW12 = on SW10 = on, SW11 = off, SW5 = off SW10 = off, SW11 = on, SW5 = off SW14 = on SW1 = on Operating Operating, SW16 = ATT Operating, SW16 = envelope SW8a, SW9a, b, c, 14 = off, Vin = 0 to VDD IOL = 1.5 mA MICO-MIC short TBO-TBI short EV6 = 0 dB -- Pin Conditions PS = 0 Digital input = GND All blocks operating, CLK = 2048, SYNC = 8 kHz, no signal -- -- IOH = -1.5 mA Value Min. -- -- -- -- VDDx0.8 0.0 -10 -20 1.40 -- -- -- -- -- 70 100 150 -10 Typ. 0.5 5.0 -- -- -- -- -- -- 1.50 -- -- -- -- -- 100 140 210 -- Max. 50 10 10 10 VDD VDDx0.2 10 20 1.60 2 2 2 2 2 140 200 300 10 Unit A mA A A V V mV mV V k k k k k k k k A
Note: Measurement conditions: s Standard Test Circuit
24
MB86437
2. AC Characteristics (1) Codec-Related Signals Parameter Digital input rise time Digital input fall time Shift clock frequency Shift clock pulse width (H) Shift clock pulse width (L) Sync frequency Sync pulse width SYNC to CLK setup time CLK to SYNC hold time CLK to DIN hold time DIN to CLK setup time SYNC to DOUT delay time CLK to DOUT delay time CLK to DOUT disable time Symbol tR tF fC tWCH tWCL fS tWSH tSX tXS tRD tDR tZD tCO tDZ BIT 1 BIT 2 to 8 "H" Conditions VS x 0.3 VS x 0.7 -law, A-law Linear VIH = VS x 0.7 VIL = VS x 0.3 -- -- -- -- -- -- Value Min. -- -- 64 128 1/fCx0.3 1/fCx0.3 -- 1/fC 100 50 50 50 -- -- -- Typ. -- -- -- -- -- -- 8 -- -- -- -- -- -- -- -- Max. 50 50 3152 3152 1/fCx0.7 1/fCx0.7 -- 62 -- -- -- -- 200 200 200 Unit ns ns kHz kHz ns ns kHz s ns ns ns ns ns ns ns
(2) Microcomputer Data-Related Signals Parameter SRC to SRD data setup time SRC to SRD data hold time SRC to STB setup time SRC pulse width (H) SRC pulse width (L) STB pulse width STB to SRC hold time LO0 to 3 delay time Shift clock frequency Reset pulse width Symbol tSSC tHSC tSCB tWH tWL tDS tHCB tLD fSCLK tWRE Pin SRD, SRC SRC, STB SRC STB STB, SRC LO0 to 3 SRC XPRST Value Min. 50 50 50 200 200 50 50 -- -- 1 Typ. -- -- -- -- -- -- -- -- -- -- Max. -- -- -- -- -- -- -- 200 2048 -- Unit ns ns ns ns ns ns ns ns kHz s
25
MB86437
3. Transmission Characteristics (1) Microphone Amp System Parameter Gain (between MICO and BBO) Gain (between JMICO and BBO) Gain (between TAUD and BBO) Signal to noise ratio (Microphone amp [1]) Signal to noise ratio (Microphone amp [2]) Signal to noise ratio (BBO) Symbol Conditions MICO = -20 dBV, 1020 Hz SW3 = on, SW1 = SW4 = SW5 = off EV0 = 0 dB JMICO = -20 dBV, 1020 Hz SW4 = on, SW1 = SW3 = SW5 = off EV0 = 0 dB TAUD = -20 dBV, 1020 Hz SW5 = on, SW1 = SW3 = SW4 = off EV0 = 0 dB Ain1 = -40 dBV (+20 dBgain), 1020 Hz SW3 = on, SW1 = SW4 = SW5 = off C message, Measured at MICO Ain2 = -40 dBV (+20 dBgain), 1020 Hz SW4 = on, SW1 = SW3 = SW5 = off C message, Measured at JMICO TAUD = -40 dBV, 1020 Hz, SW5 = on, SW1 = SW3 = SW4 = SW10 = SW11 = off, EV0 = 0 dB, C message, Measured at BBO Value Min. -1.5 Typ. -- Max. 1.5 Unit
GMB
dB
GJB
-1.5
--
1.5
dB
GTB
-1.5
--
1.5
dB
SMB
40
--
--
dB
SJB
40
--
--
dB
STB
40
--
--
dB
Note: Measurement conditions: s Standard Test Circuit (2) Reception Parameter Symbol GTR Gain Conditions: TBO = -20 dB, 1020 Hz GTE GTJ GTT PE Output power PJ Conditions Measured at RAUD EV6 = 0 dB, Measured between EAR and XEAR EV7 = 0 dB, Measured at JEAR EV8 = 0 dB, SW9b = on, SW9c = off, Measured at TONE R = 32 , Between EAR and XEAR, EV6 = 0 dB, THD = 10%, 1020 Hz R = 32 , JEAR, EV7 = 0 dB, THD = 10%, 1020 Hz TBO = -40 dBV, 1020 Hz, SW6b = SW7b = SW8b = SW9b = on, SW15 = AMP4, EV6, 7, 8 = 0 dB C message, RAUD, EAR-XEAR, Measured at JEAR SGO = -40 dBV, 1020 Hz, SW7b = on, SW15 = AMP5, C message, Measured at JEAR Value Min. -1 5 -1 -1 10.0 5.0 Typ. 0 6 0 0 -- -- Max. 1 7 1 1 -- -- mW mW dB Unit
STR Signal to noise ratio STJ
40
--
--
dB
40
--
--
dB
Note: Measurement conditions: s Standard Test Circuit 26
MB86437
(3) TONE Parameter Symbol Conditions Value Min. Typ. -14.0 Max. -16.0 Unit
GT1
Generating 1 tone, f1 = 948.1 kHz, sine wave SW2 = off, SW9b = off, SW9c = on, MDI = OPEN -12.0 EV3 = 15 dB, EV4 = -15 dB, EV9 = 0 dB, Measured at TONE Generating 2 tones, f1 = 948.1 kHz, f2 = 1219.1 kHz, simultaneous sine wave generation -12.0 SW2 = off, SW9b = off, SW9c = on, MDI = OPEN EV3 = 15 dB, EV4 = -15 dB, EV9 = 0 dB, Measured at TONE MDI = 1020 Hz, -10 dBV input SW2 = on, SW13 = off, DUAL TONE = off EV2 = 0 dB, EV3 = 15 dB, EV4 = -15 dB, EV5 = -14 dB, Measured at PTBO EV3 = 15 dB, EV4 = -15 dB, EV9 = 0 dB, SW9c = on SW2 = SW9b = off, MDI = OPEN, Generating a single tone, Measured at TONE, nth harmonic level (n = 2 to 5) EV3 = 15 dB, EV4 = -15 dB, EV5 = -15 dB, EV2 = 15 dB SW2 = on, SW9c = SW13 = off, MDI = OPEN, Generating a single tone, Measured at PTBO, nth harmonic level (n = 2 to 5) -27.0
dBV
TONE output level
GT2
-14.0
-16.0
dBV
GT3
-29.0
-31.0
dB
HTT Harmonic level HTP
--
--
-38
dB
--
--
-38
dB
(4) Reception and transmission (CODEC, Analog section) Parameter Crosstalk (Transmission reception) Crosstalk (Reception transmission) Power supply noise rejection ratio Symbol Conditions Ain1 = 1020 Hz, -8.5 dBV (0 dBgain) DIN = "H" Measurement: RAUD 1020 Hz DIN = 1020 Hz, 0 dBm 0 AIN = SGC Measurement: DOUT 1020 Hz 0 < f < 50 kHz, VDD + 30 mVOP C message AIN = SGC, DIN = ICN EV0, EV1, EV3, EV5 Gain error relative to reset value Input = 1020 Hz, -20 dBV EV2, EV4, EV6, EV7, EV8, EV9 Gain error relative to reset value Input = 1020 Hz, -20 dBV Value Min. -- Typ. -- Max. -50 Unit
CTX
dB
CTR
--
--
-50
dB
PSRR
--
22
--
dB
-0.7
--
0.7
dB
Electronic volume gain error
GEV
-1.0
--
1.0
dB
(Continued)
27
MB86437
(Continued)
Parameter Symbol Conditions SW2 = SW3 = off, EV4 = -15 dB EV2 = 0 dB, EV3 = 15 dB MDI = 1020 Hz, -30 dBV Measured at PTBO Value Min. -- Typ. -- Max. -40 Unit
Gmsw2
dB
SW1, 3, 4, 5 = off, EV0 = 0 dB Gmsw34 AIN1 or AIN2 = 1020 Hz, -30 dBV Measured at BBO Gmsw5 Mute level SW1, 3, 4, 5 = off, EV0 = 0 dB TAUD = 1020 Hz, -30 dBV, Measured at BBO
-- --
-- --
-40 -40
dB dB
SW6b = SW7b = SW8b = SW9b = SW9c = off EV6, 7, 8, 9 = 0 dB, TBO = 1020 Hz, -30 dBV Gmsw69 MDI = 1020 Hz-30 dBV, EV4 = 0 dB RAUD, EAR, XEAR, JEAR, Measured at TONE Gmsw13 Gmsw15a Gmsw15b VEV0off (EV0) SW13 = SW2 = off, EV1, 2 = 0 dB, DIN = 1020 Hz, 0 dBm0, Measured at PTBO SW15 = AMP4, TBI-TBO = short SGO = 1020 Hz, -30 dBV, Measured at JEAR SW15 = AMP5, SGI-SGO = short TBO = 1020 Hz, -30 dBV, Measured at JEAR SW3 = on, SW4 = SW5 = off MIC-MICO, SGC-XMIC = short Measured between SGC and BBO when EV0 variable SW2 = off, SW13 = on, EV2 = 0 dB SYNC = 8 kHz, CLK = 2048 kHz, DIN = ICN Measured between SGC and PTBO when EV1 variable SW2 = off, SW13 = on, EV1 = 0 dB SYNC = 8 kHz, CLK = 2048 kHz, DIN = ICN Measured between SGC and PTBO when EV2 variable Tone generation = off, SW9a, 9b = off, SW9c = on, EV4 = -15 dB, EV9 = 0 dB, MDI = open Measured between SGC and TONE when EV3 variable Tone generation = off, MDI = open, EV3 = 15 dB, EV9 = 0 dB, SW9a = 9b = off, SW9c = on Measured between SGC and TONE when EV4 variable Tone generation = off, MDI = open, EV3 = 15 dB, EV2 = 0 dB EV4 = -15 dB, SW2 = on, SW13 = off Measured between SGC and PTBO when EV5 variable
--
--
-40
dB
-- -- --
-- -- --
-40 -40 -40
dB dB dB
-10
--
10
mV
Electronic volume offset variation (amount of change for 1 step)
VEV1off (EV1)
-25
--
25
mV
VEV2off (EV2)
-25
--
25
mV
VEV3off (EV3)
-70
--
70
mV
Electronic volume offset variation (amount of change for 1 step)
VEV4off (EV4)
-300
--
300
mV
VEV5off (EV5)
-5
--
5
mV
(Continued)
28
MB86437
(Continued)
Parameter Symbol Conditions SW6b = on, SW6a = off TBI-TBO = short Measured between SGC and EAR when EV6 variable SW7b = on, SW7a = off, SW15 = AMP4 TBI-TBO = short Measured between SGC and JEAR when EV7 variable SW9b = on, SW9a, 9c = off TBI-TBO = short Measured between SGC and TONE when EV8 variable Tone generation = off, MDI = open, EV3 = 15 dB EV4 = -15 dB, SW9c = on, SW9a, 9b = off Measured between SGC and TONE Value Min. -5 Typ. -- Max. 5 Unit
VEV6off (EV6)
mV
Electronic volume offset variation (amount of change for 1 step)
VEV7off (EV7)
-5
--
5
mV
VEV8off (EV8)
-50
--
50
mV
VEV9off (EV9)
-140
--
140
mV
SW13 = off, EV2 = 0 dB, EV3 = 15 dB, VSW2off EV4 = -15 dB (SW2) EV5 = -14 dB, Tone = off, MDI = open Measured at PTBO for SW2 on and off SW1, 4, 5 = off, EV0 = 0 dB VSW3off MIC-MICO = short (SW3) Measured at BBO for SW3 on and off SW1, 3, 5 = off, EV0 = 0 dB VSW4off JMIC-JMICO = short (SW4) Measured at BBO for SW4 on and off SW1, 3, 4, 10, 11 = off, EV0 = 0 dB VSW5off TAUD = SGC (SW5) Measured at BBO for SW5 on and off SW7a, 8a, 9a = off, EV6 = -8 dB VSW6off TBI-TBO = short, EV7 = -3 dB (SW6b) Measured at EAR, XEAR for SW6b on and off SW6a, 8a, 9a = off, SW15 = AMP4 VSW7off EV7 = -3 dB, TBI-TBO = short (SW7b) Measured at JEAR for SW7b on and off SW6a, 7a, 9a = off VSW8off TBI-TBO = short (SW8b) Measured at RAUD for SW8b on and off SW6a, 7a, 8a, 9c = off, EV8 = 10 dB VSW9boff MDI = open, TBI-TBO = short (SW9b) Measured at TONE for SW9b on and off SW6a, 7a, 8a, 9b = off, EV9 = 6 dB VSW9off MDI = open, TBI-TBO = short (SW9c) Measured at TONE for SW9c on and off SW2 = off, EV1, 2 = 0 dB, DIN = ICN VSWDoff SYNC = 8 kHz, CLK = 2048 kHz (SW13) Measured at PTBO for SW13 on and off
-30
--
30
mV
-20
--
20
mV
-20
--
20
mV
-10
--
10
mV
Change in DC offset during mute
-10
--
10
mV
-10
--
10
mV
-20
--
20
mV
-65
--
65
mV
-300
--
300
mV
-90
--
90
mV 29
MB86437
(5) Codec Parameter Gain tracking (A to D) BTPO DOUT Gain tracking (D to A) DIN PTBO Gain tracking (A to D) (Linear) BTPO DOUT Gain tracking (D to A) (Linear) DIN PTBO Symbol Conditions 1020 Hz, -10 dBm0 Reference value (-law) 1020 Hz, -10 dBm0 Reference value (-law) EV1 = EV2 = 0 dB 1020 Hz, AFST-13 dB Reference value +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0
AFST to AFST-43 dB
Value Min. -0.3 -0.5 -1.0 -0.3 -0.5 -1.0 -0.3 -0.5 -1.0 -0.3 -0.5 -1.0 24.0 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 Max. 0.3 0.5 1.0 0.3 0.5 1.0 0.3 0.5 1.0 0.3 0.5 1.0 -- -- 0.20 0.8 -- -- -- 0.30 1.10 -- -- 1.0
Unit dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
GTX
GTR
GTXL
AFST-43 to AFST-53 dB AFST-53 to AFST-58 dB
GTRL
1020 Hz, AFSR-13 dB AFSR-43 to AFSR-53 dB Reference value EV1 = EV2 = 0 dB
AFSR-53 to AFSR-58 dB
AFSR to AFSR-43 dB
0 to 60 Hz Transmitting frequency characteristics (A to D) BTPO DOUT 0 dBm0 1020 Hz Reference value
60 to 300 Hz -0.20 FRX 300 to 3000 Hz -0.20 3000 to 3400 Hz -0.20 3400 to 4600 Hz 4600 to 12 kHz * 32.0
0 to 300 Hz -0.30 Receiving frequency characteristics (D to A) DIN PTBO FRR 0 dBm0 1020 Hz Reference value EV1 = EV2 = 0 dB 300 to 3000 Hz -0.30 3000 to 3400 Hz -0.30 3400 to 4600 Hz 4600 to 12 kHz Transmitting absolute gain GAX (A to D) BTPO DOUT Receiving absolute gain (D to A) DIN PTBO *: 14.5 x {1 - Sin GAR 1020 Hz, 0 dBm0 (Linear: AFST-3 dB) VS = 3.0 V, Ta = +25C * 32.0 -1.0
1020 Hz, 0 dBm0 (Linear: AFSR-3 dB) EV1 = EV2 = 0 dB, VS = 3.0 V, Ta = +25C
-1.20
0
1.20
dB
(4000 - f) 1200
}
(Continued)
30
MB86437
(Continued)
Parameter Symbol 1020 Hz C message (-law) 1020 Hz C message EV1 = EV2 = 0 dB (-law) Conditions 0 to -30 dBm0 -40 dBm0 -45 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0
AFST-3 to AFST-33 dB
Value Min. 34.0 28.0 23.0 34.0 28.0 23.0 34.0 28.0 23.0 34.0 28.0 23.0 -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -72 Max. -- -- -- -- -- -- -- -- -- -- -- -- -69
Unit dB dB dB dB dB dB dB dB dB dB dB dB
dBm0C
Transmitting signal to noise ratio SDX (A to D) BTPO DOUT Receiving signal to noise ratio (D to A) DIN PTBO
SDR
Transmitting signal to noise ratio (A to D) SDXL BTPO DOUT (Linear) Recieving signal to noise ratio (D to A) SDRL DIN PTBO (Linear) Transmitting no-talk noise BTPO DOUT Receiving no-talk noise DIN PTBO Analog input level BTPO Analog output level PTBO
1020 Hz C message
AFST-43 dB AFST-48 dB
AFSR-3 to AFSR-33 dB
SDRL
1020 Hz C message EV1 = EV2 = 0 dB
AFSR-43 dB AFSR-48 dB
ICNX
C message C message EV1 = EV2 = 0 dB 1020 Hz, 0 dBm0, Ta = +25C VS = 3.0 V -law 1020 Hz, 0 dBm0, Ta = +25C VS = 3.0 V -law EV1 = EV2 = 0 dB VS = 3.0 V, Ta = +25C Linear VS = 3.0 V, Ta = +25C Linear EV1 = EV2 = 0 dB
ICNR AILU AOLU
--
-75
-70
dBm0C
0.3290 0.3739 0.4195 Vrms 0.3290 0.3739 0.4195 Vrms 0.6729 0.7647 0.8581 VOP
Analog input fullscale level AFST BTPO Analog output fullscale level PTBO AFSR
0.6729 0.7647 0.8581
VOP
31
MB86437
s TEST CIRCUIT
50 k
50 k 0.1 F
BTPO 0.1 F SGC SGI SGO AMP5 A Dout DOUT A/D
- + - +
BTPI
BBO
STA
MICO
- +
VREF
MIC XMIC
100 k Ain1 10 k
SGC MICO EV0
- + - +
100 k JMIC 10 k Ain2
AMP2 8 kHz 2048 kHz SYNC CLK PLL
AMP1
TAUD EXSD
SGC SGC SGC SGC
Din
DIN
D/A
EV1 DSCK
SWI 1024 kHz SGC TCLK MDI TONE + EV4 EV3 EV5 +
- +
SWO SGC RAUD
PTBO TBI 50 k 0.1 50 k TBO
- +
EV2 AMP4
- +
EAR 0.1 F XEAR 32 22 F JEAR 32 0.1 F TONE 10 F 600 0.1 F
- +
A
DATA LATCH
P SAVE
- +
SRD SRC STB XPRST LO0 LO1 LO2 LO3
PS
: Digital input
: Digital output
: Analog input
: Analog output
: Input/output
: V DD
: GND
Note: Insert a large bypass capacitor between VD and GND and between SGC and VS4.
32
MB86437
s ORDERING INFORMATION
Part number MB86437PFV Package 48 pins, Plastic LQFP (FPT-48P-M05) Remarks
33
MB86437
s PACKAGE DIMENSION
48 pin Plastic LQFP (FPT-48P-M05)
9.000.20(.354.008)SQ 7.000.10(.276.004)SQ
36 25
1.50 -0.10 .059 -.004
+.008
+0.20
(MOUNTING HEIGHT)
37
24
5.50 (.217) REF INDEX
8.00 (.315) NOM
Details of "A" part
48 1 12 13
LEAD No. 0.500.08 (.0197.0031) 0.18 -0.03 .007 -.001
+.003 +0.08
"A" 0.127 -0.02 .005 -.001
+.002 +0.05
0.100.10 (STAND OFF) (.004.004)
0.500.20 (.020.008) 0.10(.004) 0 10
C
1995 FUJITSU LIMITED F48013S-2C-5
Dimensions in mm (inches)
34
MB86437
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-88, Japan Tel: (044) 754-3763 Fax: (044) 754-3329 North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, U.S.A. Tel: (408) 922-9000 Fax: (408) 432-9044/9045 Europe FUJITSU MIKROELEKTRONIK GmbH Am Siebenstein 6-10 63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122 Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LIMITED #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
F9707 (c) FUJITSU LIMITED Printed in Japan
36

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